|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
TDA7303 Digital controlled stereo audio processor with loudness Features Input multiplexer: - 3 stereo inputs - Selectable input gain for optimal adaption to different sources Volume control in 1.25dB steps Loudness function Treble and bass controL Four speaker attenuatorS: - 4 independent speakers control in 1.25dB steps for balance and fader facilities - Independent mute function All functions programmable via serial I2C bus SO-28 Selectable input gain and external loudness function are provided. Control is accomplished by serial I2C bus microprocessor interface. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Tecnology, Low Distortion, Low Noise and Low DC stepping are obtained. Description The TDA7303 is a volume, tone (bass and treble) balance (Left/Right) and fader (front/rear) processor for quality audio applications in car radio, Hi-Fi and portable systems. Order codes Part number TDA7303 TDA7303TR Package SO-28 SO-28 Packing Tray Tape and reel August 2006 Rev 1 1/21 www.st.com 1 Contents TDA7303 Contents 1 Block, test & pins diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 1.2 1.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 2.3 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 3.2 3.3 3.4 3.5 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 4.2 4.3 Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data bytes (detailed description) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/21 TDA7303 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Audio switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bass and Treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3/21 List of figures TDA7303 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Loudness vs Volume Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Loudness vs. Frequency (CLOUD = 100nF) vs. Volume Attenuation . . . . . . . . . . . . . . . . 10 Loudness versus External Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Noise versus Volume/Gain Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Signal to Noise Ratio vs. Volume Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Distortion & Noise vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Signal to Noise Ratio vs. Volume Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Distortion vs. Load Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Channel Separation (L AE R) vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Input Separation (L1 AE L2, L3) vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supply Voltage Rejection vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Clipping Level vs. Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Quiescent Current vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Supply Current vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bass Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical Tone Response (with the ext. components indicated in the test circuit). . . . . . . . . 12 Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing diagram of S-bus and I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Acknowledge on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 SO-28 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4/21 1 1.1 TDA7303 5.6K C17 2.7nF 100nF C15 BIN(L) TREBLE(L) 4 SPKR ATT 25 MUTE OUT LEFT FRONT R2 Figure 1. C9 2.2F OUT(L) 17 16 12 19 18 Block diagram IN(L) C11 100nF 100nF C14 LOUD(L) BOUT(L) RB Block diagram 3x 2.2F C1 L1 SPKR ATT 23 MUTE 15 L1 VOL + LOUD BASS TREBLE LEFT INPUTS C2 L2 14 L2 C3 L3 13 L3 OUT LEFT REAR 28 SERIAL BUS DECODER + LATCHES 27 26 Block, test & pins diagrams SCL SDA DIGGND BUS INPUT SELECTOR + GAIN C4 R3 9 R3 VOL + LOUD BASS TREBLE SPKR ATT 24 MUTE OUT RIGHT FRONT RIGHT INPUTS C5 R2 10 R2 C6 R1 11 R1 3x 2.2F SPKR ATT RB MUTE 1 7 8 IN(R) 6 CREF C7 C8 2.2F 22F OUT(R) 21 LOUD(R) 100nF C12 100nF C10 5.6K R1 20 BOUT(R) BIN(R) 100nF C13 2.7nF C16 5 TREBLE(R) D98AU888 22 SUPPLY 3 OUT RIGHT REAR 2 VS AGND Block, test & pins diagrams 5/21 Block, test & pins diagrams TDA7303 1.2 Test circuit Figure 2. Test Circuit 1.3 Pins connection Figure 3. Pin Connection (Top view) 6/21 TDA7303 Electrical specifications 2 2.1 Electrical specifications Absolute maximum ratings Table 1. Symbol VS Tamb Tstg Absolute maximum ratings Parameter Operating Supply Voltage Ambient Temperature Storage Temperature Range Value 10.0 -40 to 85 -55 to +150 Unit V C C 2.2 Quick reference data Table 2. Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz Volume Control 1.25dB step Bass and Treble Control 2dB step Fader and Balance Control 1.25dB step Input gain 3.75db step1.25dB step Mute Attenuation -78.75 -14 -38.75 0 100 Quick reference data Parameter Min. 6 2 0.01 106 103 0 +14 0 11.25 Typ. 9 Max. 10 Unit V Vrms % dB dB dB dB dB dB dB 2.3 Thermal data Table 3. Symbol Rth j-pins Thermal data Parameter Thermal Resistance Junction-pins Value max 85 Unit C/W 7/21 Electrical specifications TDA7303 2.4 Table 4. Electrical characteristics Electrical Characteristcs (Tamb = 25C, VS = 9V, RL = 10K, RG = 600, all control flat (G=0), f = 1KHz unless otherwise specified) Parameter Test Condition Min. Typ. Max. Unit Symbol SUPPLY VS IS SVR Supply Voltage Supply Current Ripple Rejection 6 9 8 10 11 V mA dB 60 80 INPUT SELECTORS RII VCL SIN RL GINmin GINmax GSTEP eIN Input Resistance Clipping Level Input Separation (2) Output Load resistance Min. Input Gain Max. Input Gain Step Resolution Input Noise G = 11.25dB pin 7, 17 Input 1, 2, 3, 4 2 80 2 -1 0 11.25 3.75 2 1 50 2.5 100 K Vrms dB K dB dB dB V VOLUME CONTROL RIN Input Resistance 70 -1 70 0.5 AV = 0 to -20dB AV = -20 to -60dB Tracking Error -1.25 -3 33 75 0 75 1.25 0 80 1 80 1.75 1.25 2 2 k dB dB dB dB dB dB dB CRANGE Control Range AVMIN AVMAX ASTEP EA ET Min. Attenuation Max. Attenuation Step Resolution Attenuation Set Error SPEAKER ATTENUATORS Crange SSTEP EA AMUTE Control Range Step Resolution Attenuation set error Output Mute Attenuation 80 100 35 0.5 37.5 1.25 40 1.75 1.5 dB dB dB dB BASS CONTROL(1) Gb BSTEP Control Range Step Resolution Max. Boost/cut 12 1 14 2 16 3 dB dB 8/21 TDA7303 Table 4. Electrical specifications Electrical Characteristcs (continued) (Tamb = 25C, VS = 9V, RL = 10K, RG = 600, all control flat (G=0), f = 1KHz unless otherwise specified) Parameter Internal Feedback Resistance Test Condition Min. Typ. 44 Max. Unit K Symbol RB TREBLE CONTROL (1) Gt TSTEP Control Range Step Resolution Max. Boost/cut 13 1 14 2 15 3 dB dB AUDIO OUTPUTS VOCL RL CL ROUT VOUT Clipping Level Output Load Resistance Output Load Capacitance Output resistance DC Voltage Level 4.2 75 4.5 4.8 d = 0.3% 2 2 10 2.5 Vrms K nF W V GENERAL BW = 20-20KHz, flat output muted all gains = 0dB A curve all gains = 0dB S/N Signal to Noise Ratio all gains = 0dB; VO = 1Vrms AV = 0; VIN = 1Vrms d Distortion AV = 20dB, VIN = 1Vrms AV = 20dB, VIN = 1Vrms Sc Channel Separation left/right Total Tracking error BUS INPUTS VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge IO = 1.6mA 3 -5 +5 0.4 1 V V A V AV = 0 to -20dB -20 to -60 dB 80 V V V dB % 0.3 % % dB 1 2 dB dB eNO Output Noise(2) 2.5 5 3 106 0.01 0.09 0.04 103 0 0 1. Bass and Treble response see attached diagram (fig.22). The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network 2. The selected input is grounded thru the 2.2F capacitor. 9/21 Electrical specifications TDA7303 2.5 Figure 4. Electrical characteristics curves Loudness vs Volume Attenuation Figure 5. Loudness vs. Frequency (CLOUD = 100nF) vs. Volume Attenuation Figure 6. Loudness versus External Capacitors Figure 7. Noise versus Volume/Gain Setting Figure 8. Signal to Noise Ratio vs. Volume Setting Figure 9. Distortion & Noise vs. Frequency 10/21 TDA7303 Electrical specifications Figure 10. Signal to Noise Ratio vs. Volume Setting Figure 11. Distortion vs. Load Resistance Figure 12. Channel Separation (L R) vs. Frequency Figure 13. Input Separation (L1 L2, L3) vs. Frequency Figure 14. Supply Voltage Rejection vs. Frequency Figure 15. Output Clipping Level vs. Supply Voltage 11/21 Electrical specifications TDA7303 Figure 16. Quiescent Current vs. Supply Voltage Figure 17. Supply Current vs. Temperature Figure 18. Bass Resistance vs. Temperature Figure 19. Typical Tone Response (with the ext. components indicated in the test circuit) 12/21 TDA7303 I2C bus interface 3 I2C bus interface Data transmission from microprocessor to the TDA7303 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data validity As shown in Figure 20, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and stop conditions As shown in Figure 21 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 3.3 Byte format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 22). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. 13/21 I2C bus interface Figure 20. Data validity on the I2C bus SDA TDA7303 SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 21. Timing diagram of S-bus and I2C bus SCL I2CBUS SDA D99AU1032 START STOP Figure 22. Acknowledge on the I2C bus SCL 1 2 3 7 8 9 SDA MSB START D99AU1033 ACKNOWLEDGMENT FROM RECEIVER Patent note: Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. 14/21 TDA7303 Software specification 4 4.1 Software specification Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7303 address (the 8th bit of the byte must be 0). The TDA7303 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 100kbits/s 4.2 Subaddress (receive mode) Table 5. 1 MSB Chip address 0 0 0 1 0 0 0 LSB Table 6. MSB 0 1 1 1 1 0 0 0 Data bytes LSB 0 1 1 0 0 1 1 1 B2 0 1 0 1 0 1 1 B1 B1 B1 B1 B1 G1 0 1 B0 B0 B0 B0 B0 G0 C3 C3 A2 A2 A2 A2 A2 S2 C2 C2 A1 A1 A1 A1 A1 S1 C1 C1 A0 A0 A0 A0 A0 S0 C0 C0 FUNCTION Volume control Speaker ATT LR Speaker ATT RR Speaker ATT LF Speaker ATT RF Audio switch Bass control Treble control Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 3.75dB steps 15/21 Software specification TDA7303 4.3 Data bytes (detailed description) Table 7. MSB 0 0 B2 B1 B0 A2 0 0 0 0 1 1 1 1 A2 A1 0 0 1 1 0 0 1 1 A1 Volume LSB A0 0 1 0 1 0 1 0 1 A0 FUNCTION Volume 1.25dB steps 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 Volume 10dB steps 0 -10 -20 -30 -40 -50 -60 -70 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 For example a volume of -45dB is given by: 00100100 Table 8. MSB 1 1 1 1 0 0 1 1 0 1 0 1 B1 B1 B1 B1 B0 B0 B0 B0 A2 A2 A2 A2 0 0 0 0 1 1 1 1 A1 A1 A1 A1 0 0 1 1 0 0 1 1 Speaker attenuators LSB A0 A0 A0 A0 0 1 0 1 0 1 0 1 FUNCTION Speaker LF Speaker RF Speaker LR Speaker RR 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 -10 -20 -30 Mute 0 0 1 1 1 0 1 0 1 1 1 1 1 For example attenuation of 25dB on speaker RF is given by: 1 0 1 1 0 1 0 0 16/21 TDA7303 Table 9. MSB 0 1 0 G1 G0 S2 S1 0 0 1 1 0 1 0 0 1 1 0 1 0 1 Software specification Audio switch LSB S0 0 1 0 1 FUNCTION Audio Switch Stereo 1 Stereo 2 Stereo 3 Not allowed Loudness ON Loudness OFF +11.25dB +7.5dB +3.75dB 0dB For example to select the stereo 2 input with a gain of +7.5dB LOUDNESS ON the 8bit string is: 0 1 0 0 1 0 0 1 Table 10. MSB 0 0 1 1 1 1 0 1 C3 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 Bass and Treble LSB C0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 FUNCTION Bass Treble -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 C3 = Sign For example Bass at -10dB is obtained by the following 8 bit string: 0 1 1 0 0 0 1 0 17/21 Package information TDA7303 5 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 23. SO-28 Mechanical Data & Package Dimensions DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 0.291 0.016 0.1 0.35 0.23 0.5 45 (typ.) 18.1 10.65 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 mm TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013 OUTLINE AND MECHANICAL DATA SO-28 8 (max.) 18/21 TDA7303 Revision history 6 Revision history Table 11. Date 04-Aug-2006 Document revision history Revision 1 Initial release. Changes 19/21 TDA7303 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 20/21 |
Price & Availability of TDA7303 |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |